Semiconductor IP Centric Design
ChipPath is the creator of a new Semiconductor IP Centric Approach mapping one Semantic-IC Specification to SoC/ASIC, FPGA and ASSP. One specification with multiple implementation choices and complete visibility into project economics and life cycle costs.

Design Simplicity
Design is distilled into three core components: I/O Channels, Subsystems, and the IPCN (IP Connection Network). At the core is semiconductor IP, which today comprises over 70% of all IC content. By focusing on design intent, optimal design choices can easily be uncovered.

Software Integration
ChipPath organizes IP to carry register definitions and memory maps, presenting them on connectors for use by software execution engines (CPU, GPU, DSP). This integration automates address map generation used in drivers and software.

Semiconductor IP Integration
I/O Interfaces and NoC (Network-on-Chip) Connectors provide the hooks for assembly automation. I/O Channels bring in protocols (like PCI Express, DDR3, Interlaken, USB, etc.) and present their data to the core NoC Connectors (AMBA, AXI4, OCP-IP, Avalon-ST, etc.). IP Integration assigns connectors and their traffic patterns to buses which in turn are generated into chip specific Bus-Fabrics (low-end) or NoC-RTL (high-performance).

Subsystems and Analog IP
IP-based design organizes the core into subsystems with NoC Connectors. Analog IP simply brings non-digital signals into the chip, converting and presented as streams of digital data onto connectors. Streams in turn are stored in memory, accessed through the fabric by subsystems for processing.

Our Products
ChipPath's IP Directory spans over 14,000 pieces of IP. Behind this data are models for over 80 bus protocols, 60 I/O electrical standards, 8,000 FPGAs, and semiconductor nodes from 14nm to 0.35um. Our RFQ tools define a Semantic-IC Specification and maps it to FPGAs and ASICs complete with a life cycle economic comparison. ChipPlanner drives design into the implementation phase with Semiconductor IP-centric floorplanning.